1. Field of the Invention
The present invention relates to a semiconductor device using an SOI (Silicon On Insulator) in which a buried oxidation film and a surface silicon layer are provided on a support substrate made of silicon and a plurality of semiconductor components are formed on the buried oxidation film, and to a method of fabricating the same.
2. Description of the Related Art
The SOI substrate is a substrate that a buried oxidation film and a surface silicon layer are formed on a support substrate made of silicon. The semiconductor device fabricated using such SOI substrate has a lot of advantages compared with a semiconductor device fabricated with bulk silicon. For instance, these advantages are in that the semiconductor device with the SOI substrate has high resistance to temperature and radiation, capability of realizing quick operation with ease, low power consumption, and so on.
Hereinafter, the structure of a semiconductor device using a conventional SOI substrate will be described with FIG. 36.
FIG. 36 is a sectional view showing the enlarged principal portion of an IC chip which is the semiconductor device using the conventional SOI substrate.
In an SOI substrate 1, a buried oxidation film 3 is provided on a support substrate 2 made of silicon and a surface silicon layer is provided on the buried oxidation film 3. However, in FIG. 36, the surface silicon layer is etched to form into a plurality of island-shape component regions and impurities are implanted into each component region and diffused to form a lightly doped N region 13 and a lightly doped P region 15.
A P channel field effect transistor (hereinafter referred to as xe2x80x9ca P channel FETxe2x80x9d) 33 and an N channel field effect transistor (hereinafter referred to as xe2x80x9can N channel FETxe2x80x9d) 35 are provided respectively on the lightly doped N region 13 and the lightly doped P region 15 isolated from each other by an insulating film 39.
In the P channel FET 33, a gate electrode 18 is formed above the center of the lightly doped N region 13 with a gate oxidation film 17 therebetween, and a P drain layer 23 and a P source layer 25 are formed respectively on either side of the gate electrode 18. The gate electrode 18, the P drain layer 23, and the P source layer 25 are respectively provided with metal electrodes (interconnection electrodes) 21 extending onto the insulating film 39 through contact holes 31.
In the N channel FET 35, a gate electrode 18 is formed above the center of the lightly doped P region 15 with a gate oxidation film 17 therebetween, and an N drain layer 27 and an N source layer 29 are formed respectively on either side of the gate electrode 18. The gate electrode 18, the N drain layer 27, and the N source layer 29 are also respectively provided with metal electrodes (interconnection electrodes) 21 extending onto the insulating film 39 through contact holes 31.
Incidentally, since the metal electrodes (interconnection electrodes) connecting with the gate electrodes 18 of the P channel FET 33 and the N channel FET 35 are respectively provided at positions in a section different from FIG. 36, they are not shown in FIG. 36.
Moreover, pad portions for providing input/output terminals are formed at the metal electrodes 21 connecting with the outside out of a number of metal electrodes 21 through the illustration thereof is omitted.
Though the P channel FET 33 and the N channel FET 35 are inverse in conduction type of the lightly doped region, the drain layer, and the source layer, they have a common basic structure. The pair of P channel FET 33 and N channel FET 35 constitute a CMOS transistor.
A passivation film 40 is provided on the entire top face of the IC chip except for the pad portions as a protection film.
In FIG. 36, only one pair of CMOS transistors is shown, but a number of CMOS transistors, other FETs, bipolar transistors, resistors, or capacitors are provided in an IC chip in use. All of these are, of course, made by the SOI technology.
When the IC chip which is the semiconductor device using the aforesaid SOI substrate is operated, it is necessary to take notice that the support substrate must be grounded or biased. For instance, the support substrate 2 needs to be grounded or biased in a case of the IC chip shown in FIG. 36. Thereby, the operation of the IC chip can be stabilized.
The above is important for a problem when the IC chip is mounted on a lead frame, a circuit board, or the like of a package.
There are two kinds of methods of mounting the IC chip, broadly divided into the face up mounting method and the face down mounting method.
The face up mounting method means that the IC chip is mounted on a mounting substrate such as a lead frame, a circuit board or the like of a package with the component face of the IC chip placed upward, and terminals (conducting to the aforesaid pad portions) provided on the component face of the IC chip and terminals on the mounting substrate side are connected by wire bonding.
The face down mounting method means that bumps or the like which are projections conducting to the aforesaid pad portions are formed on the component face of the semiconductor IC chip, and the face is placed downward directly contacting lead electrodes (conduction patterns) on the mounting substrate to be electrically connected and adhered.
According to the face up mounting method, the rear face (the side opposite to the component face) of the IC chip, that is, the rear face of the support substrate can be electrically connected with the grounded portion on the mounting substrate. Accordingly, in a case of the IC chip shown in FIG. 36, the support substrate 2 can be electrically and preferably connected with the grounded portion on the mounting substrate side to ground by adding a step for obtaining an excellent electrical contact with the grounded portion on the mounting substrate side on the rear side of the support substrate 2 of the SOI substrate 1.
However, according to the above mounting method, there is a problem that the potential of the support substrate of the IC chip is limited to the ground potential on the mounting substrate side. Accordingly, in the IC chip using the SOI substrate, even though a multi-power circuit capable of properly using a plurality of voltages can be constituted, the bias voltage of the support substrate can not be set freely, therefore there is a problem that the advantage of the multi-power circuit is not taken.
Further, in the face down mounting method, since the rear surface of the support substrate and the lead electrode formation face of the mounting substrate such as a lead frame or the like are not in contact with each other, it is difficult for the support substrate to be biased or grounded and it is hard to obtain an electrical contact between the mounting substrate and the support substrate. Therefore, there is a problem that the potential of the support substrate gets into a floating state.
The present invention is made to solve the aforesaid problem when a semiconductor device (an IC chip) with an SOI substrate is used, and its object is to make a support substrate of the semiconductor device with the SOI substrate easily grounded or biased by any mounting method.
To achieve the above object in this invention, as descried above, the semiconductor device in which a plurality of semiconductor components isolated from each other by an insulating film are provided on a buried oxidation film of the SOI substrate that the buried oxidation film is provided on the support substrate made of silicon is structured as following. Moreover, the present invention also provides the method of easily fabricating the semiconductor device.
More specifically, in the semiconductor device according to the present invention, a substrate contact hole through the insulating film and the buried oxidation film is provided at a region isolated from each semiconductor component by the insulating film, and a heavily doped diffusion layer of which the conduction type is the same as that of the support substrate is formed in the surface of the support substrate within an opening made by the substrate contact hole. A metal electrode filled in the substrate contact hole to be electrically connected with the heavily doped diffusion layer with a pad portion extending onto said insulating film is provided.
In the semiconductor device according to the present invention, since the pad portion of the metal electrode electrically connected with the support substrate through the heavily doped region is provided on the component face, the support substrate can be easily grounded or biased by connecting the pad portion to a connecting terminal or a lead electrode on the mounting substrate side when the semiconductor device is mounted on the mounting substrate such as a lead frame or the like.
In the above semiconductor device, it is preferable to be provided with a protection film for covering each semiconductor component and a connecting electrode connecting with the pad portion from the top of the protection film through an opening provided in the protection film.
When the support substrate forms into a square or a rectangle, the connecting electrode is preferably arranged along the periphery of the support substrate.
Moreover, a difference in depth level is provided in the substrate contact hole by making the opening in the insulating film forming the substrate contact hole larger than the opening in the buried oxidation film, thereby enhancing adherence of the metal electrode made of aluminum or the like.
In the above semiconductor device, the plurality of semiconductor components are made to be field effect transistors of single drain type in which gate electrodes, drain layers and source layers on both sides of the gate electrodes are formed above a plurality of component regions made of a surface silicon layer of the SOI substrate respectively with gate oxidation films therebetween, and the gate electrodes, the drain layers, and the source layers are respectively provided with metal electrodes extending onto the protection film.
Alternatively, the plurality of the semiconductor components may be field effect transistors having side walls on both sides of the gate electrodes and lightly doped drain layers are formed under the side walls.
Further, the plurality of the semiconductor components may be field effect transistors in which offset regions are provided between the gate electrodes and the drain layers.
A method of fabricating a semiconductor device according to the present invention is the method of fabricating the aforesaid semiconductor device according to the present invention and has the following steps.
(1) An SOI substrate in which a surface silicon layer is formed above a support substrate made of silicon with a buried oxidation film therebetween is prepared.
(2) A plurality of independent component regions made of the surface silicon layer are formed by selectively etching the surface silicon layer of the SOI substrate.
(3) A plurality of lightly doped P regions or N regions are formed by selectively ion-implanting impurity atoms of which the conduction type is P-type or N-type into the plurality of the component regions.
(4) The impurity atoms in each lightly doped P or N region are diffused by heat treatment.
(5) A gate electrode is formed on each lightly doped P or N region with a gate oxidation film therebetween.
(6) A drain layer and a source layer are formed by selectively ion-implanting impurity atoms of which the conduction type is opposite to that of the lightly doped P or N region into both sides of the gate electrode of each lightly doped P or N region.
(7) A substrate contact hole is formed on the support substrate by selectively etching the buried oxidation film.
(8) A heavily doped diffusion layer is formed by ion-implanting impurity atoms of which the conduction type is the same as that of the support substrate into a portion of the support substrate exposed within the substrate contact hole.
(9) A component contact hole is formed at a position independently corresponding to each gate electrode, drain layer, and source layer of each component region by forming an insulating film on the entire top face of the support substrate and thereafter performing photo-etching treatment, a forming a contact hole also at a position corresponding to the substrate contact hole.
(10) An independent metal electrode is formed for each contact hole by forming a metal electrode layer on the entire top face of the insulating film and in all the contact holes and thereafter performing photo-etching treatment, and simultaneously forming a pad portion extending onto the insulating film at the metal electrode formed in the substrate contact hole (a step of forming a metal electrode).
Alternatively, the step (6) can be replaced with the following each step.
A lightly doped drain layer is formed by selectively ion-implanting impurity atoms of which the conduction type is opposite to that of the lightly doped P or N region into both sides of the gate electrode of each lightly doped P or N region.
Side walls made of silicon oxidation film are formed on both side faces of each gate electrode.
A drain layer and a source layer are formed by selectively ion-implanting impurity atoms of which the conduction type is the same as that of the lightly doped drain layer into regions outside the side walls on both sides of the gate electrode of each lightly doped P or N region.
Further, the step (6) may be replaced with the following each step.
An offset region is formed by selectively ion-implanting impurity atoms of which the conduction type is opposite to that of the lightly doped P or N region into one side of the gate electrode of each lightly doped P or N region;
The impurity atoms in the offset region are diffused by performing heat treatment.
A drain layer and a source layer are formed by selectively ion-implanting impurity atoms of which the conduction type is the same as that of the offset region into regions on both sides of the gate electrode of each lightly doped P or N region except for the offset region.
In such method of fabricating the semiconductor device, it is preferable that a protection film is formed on the entire top face of the insulating film and each metal electrode, an opening is formed at a position in the protection film corresponding to the pad portion after the step of forming the metal electrode, and a connecting electrode connecting with the pad portion from the top of the protection film through the opening is formed.
Moreover, in the step (9) above described, it is preferable that a contact hole larger than the substrate contact hole is formed at a position corresponding to the substrate contact hole when the contact hole is formed in the step of forming the contact hole in the insulating film.